1. Field of the Invention
The invention disclosed herein relates generally to the structure and manufacturing process of a memory cell. More particularly, this invention relates to a novel cell structure and manufacturing process of a write once programmable memory.
2. Description of the Prior Art
In order to reduce cost and to shorten the time-to-market of integrated circuit (IC) products, the design houses are increasingly relying on the readily available foundry processes to carry out the prototyping and manufacturing. However, the device features that are tailored for post-package trimming require additional intellectual property (IP) modules or fuse. These IP modules may include one time programmable (OTP) memory or the electrical erasable programmable read only memory (EEPROM) provided by the foundry with additional costs. In the case of fuse, fuse-trimming using dedicated testing equipment with specific test configuration setup and high current is required. All these extra processing or testing requirements cause delays for shipping the products to the market and also increase the production costs. For these reasons, it is desirable to reduce as much as possible the requirements for post-packaging trimming and testing of these device features.
However, conventional techniques of configuring and designing such OTP memory or EEPROM cell for IC devices require complex processing. In U.S. Pat. No. 4,698,900 a method for making a non-volatile memory with dielectric filled trenches was disclosed. The invention provides a cross point EPROM array that has trenches to provide improved isolation between adjacent buried N+ bit-lines at locations where the adjacent buried N+ bit-lines are not separated by a FAMOS transistor. This results in improved leakage current, improved punch-through voltage characteristics, and in improved programmability for the cell. In another U.S. Pat. No. 6,215,140, Reisinger, et al. disclosed an electrically programmable non-volatile memory cell configuration. The semiconductor substrate is of the first conductivity type. Trenches are aligned to be parallel to one another and are incorporated in the semiconductor substrate, and first address lines run along the sidewalls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric. U.S. Pat. No. 6,584,029 disclosed a one-time programmable memory using fuse/anti-fuse and a vertically oriented fuse unit memory cell. The one-time programmable (“OTP”) memory includes one or more memory arrays stacked on top of each other. The OTP memory array is a cross-point array where unit memory cells are formed at the cross-points. The unit memory cell may include a fuse and an anti-fuse in series with each other or may include a vertically oriented fuse. Programming the memory may include the steps of selecting unit memory cells, applying a writing voltage such that critical voltage drop across the selected cells occur. This causes the anti-fuse of the cell to break down to a low resistance. The low resistance of the anti-fuse causes a high current pulse to be delivered to the fuse, which in turn melts the fuse to an open state. Reading the memory may include the steps of selecting unit memory cells for reading, applying a reading voltage to the selected memory cells and measuring whether current is present or not.
The above patented memory cell configurations however does not provide a solution to allow for application of standard foundry processes to enable low-cost post-packaging trimming requirements. Therefore, a need still exists in the art to provide an improved memory configuration and manufacturing methods to provide the one-time programmable memory cells using standard foundry process such that the above discussed difficulties as now encountered in the prior art can be resolved.